The invention relates to integrated circuits, and more particularly to a high threshold PMOS transistor utilizing a surface-channel process.
In certain integrated circuit designs, a PMOS transistor with high Vt is required to guarantee a zero through-current in normal circuit operation. This has been accomplished by the use of a xe2x80x9cnaturalxe2x80x9d Vt buried channel PMOS device. However most present day CMOS technology uses surface-channel PMOS transistors, therefore an alternative method is required.
For traditional xe2x80x9cburied-channelxe2x80x9d PMOS devices, the high Vt is easy to make. When the PMOS gate material is N+-doped polysilicon, a boron Vt adjust implant is usually required to reduce the Vt to the desired voltage, the xe2x80x9cnaturalxe2x80x9d Vt (without Vt-adjustment implant) is too high for optimum circuit performance. For a buried-channel PMOS process, the Vt-adjust implant may be blocked from those transistors that need the high Vt, and both high and low Vt devices are produced simultaneously. If the natural PMOS Vt is too high, an extra mask and implant will produce a device with the correct Vt. For surface-channel PMOS devices, obtaining high Vt is more difficult. For these devices, the PMOS gate is P+ doped, so the xe2x80x9cnaturalxe2x80x9d device has a very low Vt.
The invention provides a method for building high Vt PMOS devices in an otherwise surface-channel process without adding any process steps. A buried-channel PMOS device is fabricated simultaneously with a surface-channel device if the gate is doped N-type while the NMOS gates are doped and the P+ source/drain doping is blocked from the xe2x80x9chighxe2x80x9d P-channel device. In the normal process the xe2x80x9chighxe2x80x9d PMOS is not fully self-aligned. However, when the PMOS process includes a lightly-doped drain (PLDD), the LDD doping is self-aligned.